发明名称 RECEIVER OF SIGNAL INCLUDING TRANSPORT PACKET
摘要 <P>PROBLEM TO BE SOLVED: To develop synchronization of a multiplexing and transport packetizing apparatus. <P>SOLUTION: An apparatus for developing synchronization of a signal of an intermediate layer, such as the transport or multiplex layer of a multi-layered compressed video signal, includes, at the encoding end of a system, a counter 23 that is responsive to a system clock 22, and the counted value is embedded in the signal at the transport layer according to a predetermined schedule by a processor 13. At the receiving end of the system, an inverse transport processor 18 supplies to a system clock generator 27 a PCR and control signals from auxiliary transport data. The clock generator 27 generates, in response to these signals, a system clock signal at least synchronizing with the operation of the inverse transport processor 18. The system clock signal is supplied to a receiving system controller 26 to control the timing of processing elements. <P>COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010193522(A) 申请公布日期 2010.09.02
申请号 JP20100118159 申请日期 2010.05.24
申请人 THOMSON CONSUMER ELECTRONICS INC 发明人 DEISS MICHAEL S
分类号 H04B1/66;H04N7/173;G06T9/00;H03L7/085;H03L7/181;H04J3/00;H04L7/00;H04L7/033;H04L12/70;H04L13/08;H04N7/08;H04N7/081;H04N7/24;H04N7/62;H04N11/04;H04N19/00;H04N19/89;H04N21/236;H04N21/43;H04N21/434 主分类号 H04B1/66
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