发明名称 Readout Circuit for Rewritable Memories and Readout Method for Same
摘要 In one embodiment, a readout circuit for rewritable memories comprises a control logic unit with an input for supplying a start signal and with several outputs for providing a respective control signal as a function of start signal, a first terminal for switchable connection to a first memory cell by means of a first switch, and a second terminal for switchable connection by means of a second switch to a second memory cell, and a readout unit coupled to the control logic unit, as well as to the first and second terminals, with an output for providing an output signal as a function of a state of the first and/or the second memory cell and as a function of the control signals, wherein the readout circuit is designed for self-terminating operation in a reading mode and in a test mode. A readout method for rewritable memories is additionally provided.
申请公布号 US2010220532(A1) 申请公布日期 2010.09.02
申请号 US20100716010 申请日期 2010.03.02
申请人 AUSTRIAMICROSYSTEMS AG 发明人 FELLNER JOHANNES;SCHATZBERGER GREGOR
分类号 G11C16/26;G11C16/02;G11C29/00 主分类号 G11C16/26
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