摘要 |
<p>The arrangement has a detection block (1) comprising a transistor (P1) connected between a supply voltage connection (VDD) and a connection node (K1). Another transistor (P2) is connected between the voltage connection and another connection node (K2), where the transistors are designed as p-channel FETs. A control block (2) provides a switching signal based on voltage at the latter node and provides another switching signal through inversion of the former signal, where the former signal is supplied to a switch (N1) and the latter signal is supplied to a control connection (S1).</p> |