发明名称 |
SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND DESIGN METHOD |
摘要 |
<P>PROBLEM TO BE SOLVED: To reduce a semiconductor chip size without being restricted by a minimum pad interval. Ž<P>SOLUTION: The semiconductor wafer (1) includes wires (20) each used for short-circuiting pads (11a, 11b) to which the same signal is applied in wafer level burn-in to each other. The wires (20) are laid out outside regions of semiconductors (10a, 10b), and partially included in a dicing region (30). Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
|
申请公布号 |
JP2010192507(A) |
申请公布日期 |
2010.09.02 |
申请号 |
JP20090032444 |
申请日期 |
2009.02.16 |
申请人 |
PANASONIC CORP |
发明人 |
SOGAWA YASUO;KAWASHIMA KAZUYUKI;KAMESHIRO TOSHIHARU;SENDA TAKASHI |
分类号 |
H01L21/822;H01L21/66;H01L21/82;H01L27/04 |
主分类号 |
H01L21/822 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|