发明名称 Pattern controlled, full speed ATE compare capability for deterministic and non-deterministic IC data
摘要 Pattern controllable LFSRs or MISRs are disclosed that are able to mask indeterminate states while performing tests on DUT outputs. At appropriate times, the MISRs or the LFSRs will mask the data being input to the MISRs or the LFSRs so that indeterminate states are not received. This allows fast/complex ATE Rx memory to be replaced by slower and smaller MISR pattern memory. At the end of a test period, the LFSRs or MISRs generate signatures which are then compared to a set of possible valid signatures for non-deterministic data. A pass/fail result is produced. By masking indeterminate states, fewer valid signatures need to be stored. Masking of the MISRs or LFSRs may be based on the fact that indeterminate states and good data in a serial output data stream tend to occur in predictable patterns, or that good data may follow alignment characters. MISR or LFSR output signatures may also be employed to test individual pattern segments instead of the entire input test pattern. This expected DUT Rx data compression implementation works for one signature (deterministic) data as well.
申请公布号 US7788562(B2) 申请公布日期 2010.08.31
申请号 US20060606866 申请日期 2006.11.29
申请人 ADVANTEST CORPORATION 发明人 BRENNAN THOMAS JOSEPH;ARMSTRONG DAVID HARRY
分类号 G01R31/28 主分类号 G01R31/28
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