| 摘要 |
A phase synchronization apparatus includes an oscillator gain setting member configured to discriminate a frequency by sequentially delaying input clock signal after dividing the input clock signal at a predetermined division ratio and to generate an oscillator gain setting signal by using discriminated frequency information, and a phase locked loop (PLL) circuit configured to oscillates output clock signal having a frequency corresponding to the oscillator gain setting signal in response to the input clock signal.
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