发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 <p>PURPOSE: A method for manufacturing a semiconductor device is provided to reduce a gate tunnel leakage current by injecting foreign materials to one pair of first and second p type wells where one pair of first and second MIS transistors are formed. CONSTITUTION: One pair of first and second p type wells which first and second MIS transistors are formed is provided. A gate electrode and a gate electrode are respectively formed on the first and second p type wells. A phosphor ion is injected into a first p type well(210). A second p type well(212) is injected to arsenic ion. After the arsenic and phosphorous are injected, a sidewall is formed on the gate electrode. After the sidewall is completely formed, the arsenic is injected to the first and second p type wells. A device isolation region(201) is formed by removing a silicon nitride layer.</p>
申请公布号 KR20100095416(A) 申请公布日期 2010.08.30
申请号 KR20100078270 申请日期 2010.08.13
申请人 KABUSHIKI KAISHA HITACHI SEISAKUSHO(D/B/A HITACHI, LTD.);HITACHI ULSI SYSTEMS CO., LTD. 发明人 OSADA KENICHI;ISHIBASHI KOICHIRO;SAITOH YOSHIKAZU;NISHIDA AKIO;NAKAMICHI MASARU;KITAI NAOKI
分类号 G11C11/41;G11C11/413;G11C11/412;H01L21/8234;H01L21/8238;H01L21/8244;H01L27/088;H01L27/092;H01L27/10;H01L27/11;H03K19/00 主分类号 G11C11/41
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