发明名称 SYSTEM AND METHOD FOR A VERSATILE DISPLAY PIPELINE ARCHITECTURE FOR AN LCD DISPLAY PANEL
摘要 <p>A video processing system comprising a video frame buffer memory, a first video pipeline, a second video pipeline, a blender, and an overdrive processing unit The video frame buffer memory has a first memory region and a second memory region, the first memory region being configured to store a first video data frame and the second memory region being configured to store a second video data frame The first video pipeline is coupled to the video frame buffer memory and configured to receive and process the first video data frame The second video pipeline is coupled to the video frame buffer memory and configured to receive and process the second video data frame The blender is coupled to the first and second video pipelines and is configured to receive and blend the processed first video data frame and the processed second video data frame in a first mode of operation.</p>
申请公布号 WO2010096143(A1) 申请公布日期 2010.08.26
申请号 WO2009US68990 申请日期 2009.12.21
申请人 ZORAN CORPORATION;HE, LEI 发明人 HE, LEI
分类号 H04N9/12 主分类号 H04N9/12
代理机构 代理人
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