发明名称
摘要 An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations.
申请公布号 JP2010529648(A) 申请公布日期 2010.08.26
申请号 JP20100510378 申请日期 2008.01.17
申请人 发明人
分类号 H01L21/82;H01L21/336;H01L21/8234;H01L27/088;H01L29/00;H01L29/78;H01L29/786 主分类号 H01L21/82
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