| 摘要 |
A frame rate is improved in accordance with the number of times pixels are summed without increasing an operating frequency of a column scanning circuit, when pixel summation is performed between columns. According to the invention, a row scanner selectively controls unit pixels of a pixel array unit on a row-by-row basis. A column-by-column AD converter is provided in each of columns in the pixel array unit and converts an analog signal of each of the pixels in the rows selected by the row scanner into a digital signal. A column-by-column summer is provided in each of the columns and sums the digital signal of each of the pixels in the rows selected by the row scanner on a column-by-column basis. An input-output selector is provided between the column-by-column AD converters and the column-by-column summers, and selects the column-by-column AD converter of any arbitrary column as an input destination, while selecting the column-by-column summer of any arbitrary column as an output destination. A column scanner serially outputs summation results of the column-by-column summers by scanning columns. A controller controls the timing of the operations of the row scanner, the column-by-column AD converters, the input-output selector and the column-by-column summers.
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