| 摘要 |
An apparatus for verifying an operation of a hardware descriptor program under test includes a lexical analyzer, a parsing engine and a generator. The lexical analyzer receives input/output (I/O) information of hardware descriptor language code that represents a circuit description of an integrated circuit to be tested. The lexical analyzer performs lexical analysis on the I/O information of the hardware descriptor language code so as to generate a stream of tokens. The parsing engine interprets the stream of tokens representing the I/O information of the hardware descriptor language code based on an interpretation of rules required to test a plurality of functions capable of being executed by the integrated circuit. The generator generates verification module code based on the interpretation of the stream of tokens representing the I/O information of the hardware descriptor language code and the rules interpretation.
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