| 摘要 |
A direct access memory system includes n (n>1) memory arrays (1.1 to 1.n), a address decoder (2), a data connecting circuit (3), and a write controlling circuit (4). The address decoder (2) includes a binary decoder (5), and n-1 selectors (6.1 to 6.n1). The direct access memory system has an address bus (01) for lead in address A, k (k>1), input/output data buses (02.1 to 02.k) for data transmission, and a control bus (03) for lead in write control signals. The data is stored by bytes, each data byte D being addressable by one address A. After the address A has been set on the address bus (01), in memory arrays (1.1 to 1.n) the memory locations are activated in which the data bytes DA, DA+1, . . . , DA+k−1 are stored. The data connecting circuit (3) connects the data interfaces of the memory arrays (1.1 to 1.n) with the data buses (02.1 to 02.k) so that the first data bus (02.1) transmits the data byte DA, and simultaneously the second data bus (02.2) transmits the data byte DA+1, . . . , and simultaneously the k-th data bus (02.k) transmits the data byte DA+k−1. This parallel access memory provides parallel access to sequentially arranged data which is several bytes long, e.g. to the instruction code, within one read/write memory cycle.
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