| 摘要 |
A shift register which is capable of minimizing a spike voltage is disclosed. The shift register includes a plurality of stages, each including a plurality of nodes, a scan pulse output unit controlled according to voltages at the nodes for outputting a scan pulse and supplying it to a corresponding gate line through a scan output terminal, a carry pulse output unit controlled according to the voltages at the nodes for outputting a carry pulse and supplying it to an upstream stage and a downstream stage through a carry output terminal, a node controller for controlling voltage states of the nodes in response to a carry pulse from the upstream stage and a carry pulse from the downstream stage, and a discharging unit connected to any one of a plurality of clock transfer lines and the scan output terminal for discharging a spike voltage of the scan output terminal.
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