发明名称 |
COMPONENT FOR TERMINAL EXTENSION, USED FOR TERMINAL LAYER SETTING OF SEMICONDUCTOR CIRCUIT HAVING PLURALITY OF WIRING LAYERS |
摘要 |
PROBLEM TO BE SOLVED: To provide a terminal layer-setting method that can avoid an increase in delay time of cells or macros mounted on a substrate and set a wiring layer (terminal layer) as an extension destination of a cell or macro. SOLUTION: The terminal layer-setting method in which a computer sets a terminal layer of a semiconductor circuit having a plurality of wiring layers includes: constituting a semiconductor circuit; acquiring various information such as arrangement information related to the plurality of cells or macros mounted on the substrate from a storage means of the computer; comparing driving capability of a target cell or macro included in the acquired information with the resistance value of wiring for connecting the target cell or macro to a cell or macro as a connection destination; and setting the terminal layer being the wiring layer as an extension destination of a wiring terminal of the target cell or macro on the basis of the result of the comparison. COPYRIGHT: (C)2010,JPO&INPIT
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申请公布号 |
JP2010187005(A) |
申请公布日期 |
2010.08.26 |
申请号 |
JP20100077341 |
申请日期 |
2010.03.30 |
申请人 |
FUJITSU SEMICONDUCTOR LTD |
发明人 |
OBA HISAYOSHI |
分类号 |
H01L21/82;G06F17/50 |
主分类号 |
H01L21/82 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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