发明名称 METHOD FOR DESIGNING CELL LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 With a conventional method for designing cell layout, it is necessary to give relative positional information in advance to all cells to be arranged. Furthermore, the conventional method is troublesome because it is necessary to correct relative positional information of cells after confirming a result of temporary layout. Therefore, it takes time to obtain a layout result. To avoid these problems, cells of a specific type specified from outside, or cells satisfying specific conditions, are extracted and arranged first or limited to a layout position by specifying a layout position, then arranging the remaining cells using a general layout algorithm.
申请公布号 US2010218154(A1) 申请公布日期 2010.08.26
申请号 US20100773260 申请日期 2010.05.04
申请人 ITOH KATSUYUKI;IWAMOTO HIRONORI 发明人 ITOH KATSUYUKI;IWAMOTO HIRONORI
分类号 G06F17/50 主分类号 G06F17/50
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