发明名称 DECODER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a decoder circuit that prevents the delay of decoder output. SOLUTION: A switch 16 that is put into an ON state when a node A 60 of an NMOS region 12 is not an output channel of a selected gradation voltage, is connected to the node A 60. Thus, electric charges are accumulated on the node A 60 by a coupling capacity C1 caused in the node A 60 when the selected gradation voltage is output from an output terminal of the decoder output DECOUT, and a raised voltage is discharged by the switch 16 in the ON state. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010186048(A) 申请公布日期 2010.08.26
申请号 JP20090030044 申请日期 2009.02.12
申请人 OKI SEMICONDUCTOR CO LTD 发明人 HANYU TOMOHIRO
分类号 G09G3/36;G02F1/133;G09G3/20 主分类号 G09G3/36
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