| 摘要 |
An analog-to-digital converter 130 generates an output digital value equivalent to the difference between two analog signals. The converter 130 forms part of a set of converters. The converter receives a first analog signal and a second analog signal (V reset , V sig ) and a ramp signal (V ramp ). A clock 110 is dedicated to the converter 130, or a sub-set of converters 130. A control stage 130 enables a first counter 151 based on a comparison of the ramp signal with the first analog signal and the second analog signal. The converter 130 can be calibrated by at least one reference signal (V ref1 , V ref2 ) which is common to the set of converters 130. A-to-D conversion can include a first A-to-D conversion stage which determines a signal range, selected from a plurality of signal ranges, and a second A-to-D conversion stage which determines an M-bit digital value equivalent to the difference between the first and second analog signals by comparing the signals with a ramp signal, with the ramp signal having the signal range determined by the first analog-to-digital conversion stage. |
