| 摘要 |
<p>It is intended to provide a semiconductor device capable of solving problems of increase in power consumption and lowering in operation speed due to an increase in parasitic resistance of a surrounding gate transistor (SGT) as a three-dimensional transistor, to achieve high-speed SGT operation and low power consumption. In order to achieve this object, the present invention provides a semiconductor device which comprises: a first silicon pillar formed on a semiconductor substrate; a second silicon pillar formed on the first silicon pillar; a first insulator surrounding a part of a surface of the second silicon pillar; a gate surrounding the first insulator; a third silicon pillar formed on the second silicon pillar; a first silicide surrounding a part of a surface of the first silicon pillar; and a second silicide surrounding a part of a surface of the third silicon pillar, wherein each of a contact resistance formed by the first silicide and the first silicon pillar, and a contact resistance formed by the second silicide and the third silicon pillar, is less than a reference resistance of the semiconductor device.</p> |
