发明名称 |
Stacked power clamp having a BigFET gate pull-up circuit |
摘要 |
An electronic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs and a triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.
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申请公布号 |
US7782580(B2) |
申请公布日期 |
2010.08.24 |
申请号 |
US20070865820 |
申请日期 |
2007.10.02 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GAUTHIER, JR. ROBERT J.;LI JUNJUN |
分类号 |
H02H9/00 |
主分类号 |
H02H9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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