| 摘要 |
A resettable multi-stage sigma-delta analog-to-digital (A/D) converter enables a sampled analog signal to be resolve with fewer cycles than a resettable single sigma-delta A/D converter. The resettable multi-stage converter includes a cascade of at least two resettable sigma-delta loops having a total number of integrators and an allocation of delays, a digital decimation filter, the digital decimation filter being coupled to the at least two resettable sigma-delta loops and the digital decimation filter includes a cascade of integrators, a number of the integrators in the cascade of integrators for the decimation filter being equal to the total number of integrators in the cascade of at least two resettable sigma-delta loops and an allocation of delays in the cascade of integrators being equal to the allocation of delays in the cascade of at least two resettable sigma-delta loops, a plurality of A/D converters having a resolution that is less than a resolution of the resettable multi-stage sigma-delta A/D converter, a plurality of digital-to-analog (D/A) converters, the plurality of A/D converters and the plurality of D/A converters coupling the cascade of at least two resettable sigma-delta loops to the digital decimation filter, and a reset line coupled to the integrators in the cascade of integrators for the at least two resettable sigma-delta loops and coupled to the integrators in the cascade of integrators for the digital decimation filter.
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