发明名称 |
Interconnect structure and method of fabricating same |
摘要 |
An improved interconnect structure and method of making such a device. The improved interconnect electrically connects two otherwise separate areas on a semiconductor wafer. The interconnect preferably uses a copper conductor disposed within a trench and via structure formed in a low-k hybrid dielectric layer using a dual damascene process. Each contact region is served by a plurality of vias, each in communication with the trench conductor portion. The entry from the trench to the via is rounded for at least one and preferably all of the via structures.
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申请公布号 |
US7781892(B2) |
申请公布日期 |
2010.08.24 |
申请号 |
US20050317652 |
申请日期 |
2005.12.22 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
CHEN HSUEH-CHUNG;LOU CHINE-GIE;LIU PING-LIANG;FAN SU-CHEN |
分类号 |
H01L29/41 |
主分类号 |
H01L29/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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