发明名称 |
Structure for reduction of soft error rates in integrated circuits |
摘要 |
A structure for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.
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申请公布号 |
US7781871(B2) |
申请公布日期 |
2010.08.24 |
申请号 |
US20090483364 |
申请日期 |
2009.06.12 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CABRAL, JR. CYRIL;GORDON MICHAEL S.;RODBELL KENNETH P. |
分类号 |
H01L23/552 |
主分类号 |
H01L23/552 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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