摘要 |
A group III-V MOSFET includes metal source and drain regions that are in direct contact with the quantum well region. Such an apparatus comprises a substrate, a III-V quantum well layer formed on the substrate, a III-V barrier layer formed on the quantum well layer, a gate dielectric layer formed on the barrier layer, a gate electrode formed on the gate dielectric layer, a first metal sidewall liner formed adjacent to both the quantum well layer and the barrier layer, a second metal sidewall liner formed adjacent to both the quantum well layer and the barrier layer, a metal source region adjacent to the first metal sidewall liner, and a metal drain region adjacent to the second metal sidewall liner. |
申请人 |
INTEL CORPORATION;MAJHI, PRASHANT;GOEL, NITI;KOVESHNIKOV, SERGEI;TSAI, WILMAN;RADOSAVLJEVIC, MARKO;PILLARESITTY, RAVI;GARGINI, PAOLO |
发明人 |
MAJHI, PRASHANT;GOEL, NITI;KOVESHNIKOV, SERGEI;TSAI, WILMAN;RADOSAVLJEVIC, MARKO;PILLARESITTY, RAVI;GARGINI, PAOLO |