发明名称 CLOCK EXTRACTING CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To obtain a symptom of error occurrence prior to error occurrence. <P>SOLUTION: A clock extracting circuit includes: a clock recovery circuit 11 for recovering a clock signal CK1 related to a data input signal Din from the data input signal Din; a sampling clock generating circuit 12 for generating one or more sampling clock signals CK2, CK3 each being synchronized with the recovered clock signal CK1 and having a fixed phase difference from the recovered clock signal CK1; a sample/hold circuit 13 for sampling/holding the data input signal Din in accordance with the one or more sampling clock signals CK2, CK3 and the recovered clock signal CK1; and an error determining circuit 14 for outputting an error symptom signal Ep when all logic values of sampling results in the sample/hold circuit 13 are different from one another. <P>COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010183429(A) 申请公布日期 2010.08.19
申请号 JP20090026190 申请日期 2009.02.06
申请人 RENESAS ELECTRONICS CORP 发明人 WAKAYAMA YASUSHI
分类号 H04L7/02;H04L1/00;H04L25/08 主分类号 H04L7/02
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