发明名称 Method for fabricating a transistor having vertical channel
摘要 A semiconductor device including vertical channel transistor and a method for forming the transistor, which can significantly decrease the resistance of a word line is provided. A vertical channel transistor includes a substrate including pillars each of which has a lower portion corresponding to a channel region. A gate insulation layer is formed over the substrate including the pillars. A metal layer having a low resistance is used for forming a surrounding gate electrode to decrease resistance of a word line. A barrier metal layer is formed between a gate insulation layer and a surrounding gate electrode so that deterioration of characteristics of the insulation layer is prevented. A world line is formed connecting gate electrodes formed over the barrier layer to surround the lower portion of each pillar.
申请公布号 US7776694(B2) 申请公布日期 2010.08.17
申请号 US20080165427 申请日期 2008.06.30
申请人 HYNIX SEMICONDUCTOR INC. 发明人 JANG SE-AUG;YANG HONG-SEON;CHO HEUNG-JAE;SUNG MIN-GYU;KIM TAE-YOON;KIM SOOK-JOO
分类号 H01L21/336;H01L21/3205 主分类号 H01L21/336
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