发明名称 |
PHASENEINSTELLVORRICHTUNG UND VERFAHREN FÜR EIN SPEICHERBAUSTEIN-SIGNALISIERUNGSSYSTEM |
摘要 |
A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory component, wherein the first signal comprises a first symbol and the second signal comprises a second symbol. A first circuit of the memory controller receives the first signal by sampling the first symbol using a first timing offset relative to a reference clock signal, and a second circuit of the memory controller receives the second signal by sampling the second symbol using a second timing offset relative to the reference clock signal. The first timing offset is independent of the second timing offset. |
申请公布号 |
AT477634(T) |
申请公布日期 |
2010.08.15 |
申请号 |
AT20020802180T |
申请日期 |
2002.10.22 |
申请人 |
RAMBUS INC. |
发明人 |
HAMPEL, CRAIG;PEREGO, RICHARD;SIDIROPOULOS, STEPHANOS;TSERN, ELY;WARE, FREDRICK |
分类号 |
H04L5/16;G06F1/04;G11C7/10;G11C7/22;G11C11/4078;H04L7/00 |
主分类号 |
H04L5/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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