| 摘要 |
<p>One pixel is provided with a first pixel electrode (17a) electrically connected to a first transistor (12), and a second pixel electrode (17b) connected to the first pixel electrode (17a) with a capacitor therebetween. Retention capacity wiring (18j) is formed on the same layer where a data signal line (15j) is formed, a second transistor (212c) is electrically connected to the retention capacity wiring (18j) and the first pixel electrode (17a), and the third transistor (212b) is electrically connected to the retention capacitive wiring (18j) and the second pixel electrode (17b). Thus, in a capacitively coupled active matrix substrate having a transistor for electric discharge, deterioration of aperture ratio and load increase of a gate bus line (scanning signal line) are suppressed.</p> |
