发明名称 NONVOLATILE SEMICONDUCTOR MEMORY
摘要 <p><P>PROBLEM TO BE SOLVED: To reduce a standby current of a chip by reducing a cut-off current of a MOS transistor of a bit line sense amplifier during a standby state of the chip, in a nonvolatile semiconductor memory. <P>SOLUTION: The memory includes a memory circuit part 10 including a bit line sense amplifier 12 detecting data read out from a memory cell array, and an internal voltage drop power supply-generating circuit 20 which generates internal voltage drop power supply voltage in which external power supply voltage is dropped and which supplies it to at least the bit line sense amplifier. The internal voltage drop power supply-generating circuit generates first internal voltage drop power supply voltage required for operation of the bit line sense amplifier when a memory chip is in an active state, and generates second internal voltage drop power supply voltage lower than the first internal voltage drop power supply voltage when the memory chip is in a standby state. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2010176731(A) 申请公布日期 2010.08.12
申请号 JP20090015782 申请日期 2009.01.27
申请人 TOSHIBA CORP 发明人 FUTAYAMA TAKUYA;TOKIWA NAOYA
分类号 G11C16/06;G11C16/04 主分类号 G11C16/06
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