发明名称 PIPELINED MICROPROCESSOR WITH FAST NON-SELECTIVE CORRECT CONDITIONAL BRANCH INSTRUCTION RESOLUTION
摘要 A microprocessor includes a pipeline of stages for processing instructions and first and second types of conditional branch instruction includable by a program. The microprocessor makes a prediction of conditional branch instructions of the first type and flushes the pipeline of instructions if the prediction is subsequently determined to be incorrect, thereby incurring a branch misprediction penalty related to processing of conditional branch instructions of the first type. The microprocessor always correctly resolves conditional branch instructions of the second type without making a prediction of conditional branch instructions of the second type, thereby avoiding ever incurring a branch misprediction penalty related to processing of conditional branch instructions of the second type.
申请公布号 US2010205407(A1) 申请公布日期 2010.08.12
申请号 US20090481511 申请日期 2009.06.09
申请人 VIA TECHNOLOGIES, INC. 发明人 HENRY G. GLENN;PARKS TERRY;BEAN BRENT
分类号 G06F9/38;G06F9/30 主分类号 G06F9/38
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