| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that suppresses an error when adjusting a phase difference by eliminating a difference in propagation delay between a clock signal propagated from a first clock signal and a clock signal propagated from a second clock signal (CK2) among clock signals input to a phase comparing circuit. SOLUTION: The semiconductor integrated circuit includes: a first circuit operating based upon the first clock signal; a second circuit operating based upon the second clock signal; the phase comparing circuit which compares the phase of a signal corresponding to the first clock signal with the phase of a signal corresponding to the second clock signal; a first level shift circuit interposed in a path through which the first clock signal reaches the phase comparing circuit and varying the voltage level of the first clock signal; and a second level shift circuit interposed in a path through which the second clock signal reaches the phase comparing circuit and having the same circuit configuration with the first level shift circuit. Wherein, the phase difference between the first clock signal and second clock signal is adjusted according to a comparison result of the phase comparing circuit. COPYRIGHT: (C)2010,JPO&INPIT
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