发明名称 |
Lock and Key Through-Via Method for Wafer Level 3D Integration and Structures Produced |
摘要 |
A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.
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申请公布号 |
US2010200992(A1) |
申请公布日期 |
2010.08.12 |
申请号 |
US20100763596 |
申请日期 |
2010.04.20 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
PURUSHOTHAMAN SAMPATH;ROTHWELL MARY E.;SHAHIDI GHAVAM GHAVAMI;YU ROY RONGQING |
分类号 |
H01L23/522;H01L21/768 |
主分类号 |
H01L23/522 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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