| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock frequency divider circuit that executes phase adjustment of an output clock signal during frequency division while considering the communication timing of an operation circuit, and to provide a clock frequency dividing method. <P>SOLUTION: The clock frequency divider circuit 100 has a mask control circuit 20 that generates a count value 55 indicating a relative phase of communication timing with respect to an input clock signal (a clock S) on the basis of a clock pulse of the input clock signal, a communication timing signal 26, and a reset value 81 generated according to a phase adjustment signal 60, and also, generates a mask signal 25 for masking clock pulses with respect to the clock pulses other than those for communication timing out of M clock pulses of the input clock signal on the basis of the count value 55. Further, the clock frequency divider circuit has a mask circuit 10 for masking the clock pulses of the input clock signal according to the mask signal 25. <P>COPYRIGHT: (C)2010,JPO&INPIT |
