发明名称 Low thermal resistance package
摘要 Techniques for arranging ball grid arrays for producing low thermal resistance packages. One embodiment is for a ball grid array package that comprises a substrate, the substrate having a top surface and a bottom surface. A plurality of thermal balls are coupled to the bottom surface of the substrate, and at least one vias is positioned between every pair of the plurality of thermal balls. Other embodiments contemplate a ball grid array comprising thermal balls with a via located between every four thermal balls, wherein at least one vias is substituted for a thermal ball in the ball grid array.
申请公布号 US7772705(B2) 申请公布日期 2010.08.10
申请号 US20050049386 申请日期 2005.02.02
申请人 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 发明人 KAIZUKA MASAO
分类号 H01L23/48 主分类号 H01L23/48
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