发明名称 Memory system and memory device
摘要 According to one embodiment, a first memory device is configured to receive write data from a controller and transmit read data to the controller via a first data pin included in the first memory device. The second memory device is configured to receive write data from the controller and transmit read data to the controller via a second data pin included in the second memory device. A redelivery module within the first memory device is configured to receive an address and a command output from the controller via a predetermined signal line, and output the address and the command to the second memory device via remaining first data pin.
申请公布号 US7774535(B2) 申请公布日期 2010.08.10
申请号 US20090428370 申请日期 2009.04.22
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 NAKAMURA NOBUTAKA
分类号 G06F12/00 主分类号 G06F12/00
代理机构 代理人
主权项
地址