发明名称 CLOCK GENERATING CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To start or stop a main clock and a sub-clock in an optional sequence. <P>SOLUTION: A main (sub) clock circuit includes: a first (second) capacitor; a first (second) current-supply circuit to supply, a first (third) current for charging at a predetermined-current value or a second (fourth) current for discharging at a predetermined-current value to the first (second) capacitor; a first (second) charge/discharge control circuit to output a first (second) control signal for switching the first (third) current and second (fourth) current which are supplied to the first (second) capacitor from the first (second) current-supply circuit when a voltage across the first (second) capacitor has reached a first (third) reference voltage or a second (fourth) reference voltage higher than the first (third) reference voltage; and a first (second) output circuit to output a main (sub) clock according to the first (second) control signal. The first capacitor has one end connected to first potential. The second capacitor has one end to which the main clock is input. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2010171727(A) 申请公布日期 2010.08.05
申请号 JP20090012282 申请日期 2009.01.22
申请人 SANYO ELECTRIC CO LTD;SANYO SEMICONDUCTOR CO LTD 发明人 OYAGI MITSURU;NISHI TOMOAKI
分类号 H03K5/00;G06F1/12;H03K4/06 主分类号 H03K5/00
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