| 摘要 |
<P>PROBLEM TO BE SOLVED: To shorten a data transfer time and to reduce a circuit scale by incorporating a logic for rearranging transfer source data to generate a transfer destination start address, into a data rearrangement circuit. Ž<P>SOLUTION: In a DMA control device for continuously performing DMA transfer through a plurality of N byte width buses, a conversion register is configured of N pieces of registers for holding one byte data in each byte lane, and a data rearrangement control part is configured to shift a byte position in each byte lane about transfer source data, and to shift the data to a conversion register, and a buffer address generation part is configured to compare the low order bits of a transfer source address with those of a transfer source address only of the square root of N, and to generate a start address for designating the address of an internal buffer in which transfer data in a read/write cycle should be written. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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