CURRENT SWITCH CELL AND DIGITAL/ANALOG CONVERTER

摘要

Two D flip-flops (D-FFMA, D-FFMB) divide a digital input signal (DM) into two and output two retimed half-rate signals (DMR-A, DMR-B) by means of a clock signal (CLK) and complementary clock signal (CLKB). A first and second switch (SM1, SM2) are driven by these two half-rate signals (DMR-A, DMR-B), and a third and fourth switch (SM3, SM4) are driven by a select signal (SW) and complementary select signal (SWB) which have the same frequency as the clock signal (CLK) but a different phase. Due to this, a current fed from a current source (1) to a load (4) is made into a current signal corresponding to a converted frequency double the frequency of the clock signal (CLK).