| 摘要 |
PROBLEM TO BE SOLVED: To improve performance of a whole system by synchronizing communication and computations between stacked computing LSIs. SOLUTION: Each of a COMLSI and an LGLSI 1 which are stacked has a PLL which multiplies a crystal oscillator clock signal, a clock pulse generator which distributes the clock signal, and flip-flop circuits. The LGLSI 1 has a DLL circuit composed of a clock phase comparator (CMP), a delay controller (Delay_CTL), and a delay chain (Delay_Chain). In order to synchronize the communication and computations of the COMLSI and LGLSI 1, a synchronization reference clock signal is transmitted from the COMLSI to the LGLSI 1 via a through-electrode (TVCLK). The internal clock signal of the LGLSI 1 is synchronized with the synchronization reference clock signal from the COMLSI by the DLL circuit. COPYRIGHT: (C)2010,JPO&INPIT
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