| 摘要 |
A register file comprising a plurality of register entries for storing data values for use in the execution of data processing instructions is provided, and comprises at least one write port and at least one read port, and circuitry responsive to a write request received at said at least one write port to update one of said plurality of register entries identified by an address specified by said write request with a data value specified by said write request. The register file also comprises further circuitry responsive to a received control signal to set at least a portion of a predetermined register entry to a predetermined value. In this way, certain register file updating instructions can be executed in parallel with other instructions without the need for additional full write-ports as would be required for typical dual-issue, thereby reducing area and routing complexity and cost compared with the use of an additional write-port due to the lower gate count required by the proposed further circuitry.
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