| 摘要 |
A parallel-to-serial converter selects variable-ml-bit parallel dummy data from m-bit parallel dummy data (0<=m1<=m) together with a n-bit parallel data signal synchronized with a first clock signal having a first frequency, and converts the selected (n+m1)-bit parallel data into a (n+m1)-bit serial data signal synchronized with a second clock signal having a frequency (n+m1) times the first frequency. A serial-to-parallel converter circuit selects n-bit serial data from the (n+m1) parallel data signal and converts the n-bit serial data into a n-bit parallel data signal synchronized with the first clock signal. |
