发明名称 Integrated circuit with multidimensional switch topology
摘要 An FPGA needs extremely large numbers of switches in its wiring architecture and therefore shows low logic density and low operating speed. This tendency becomes increasingly evident with high integration FPGAs. 3-dimensional FPGAs are getting attention for potential improvements in their operating speed and logic density. However, 3-dimensional integration processes have poor yield and are difficult to adapt for the production of devices with fine features. In addition, difficulty in heat radiation imposes limits on the number of stacks. The present invention exploits advantages of the 3-dimensional FPGA to deliver FPGAs with high speed/high integration and which resolves difficulty in manufacturing processes. The present invention solves problems by proposing a design method for an FPGA in which a high dimensional FPGA switch topology is embedded in a lower dimensional integrated circuit and a semiconductor integrated circuit including an FPGA in which a high dimensional FPGA switch topology is embedded in a lower dimensional integrated circuit.
申请公布号 US7768314(B2) 申请公布日期 2010.08.03
申请号 US20050596011 申请日期 2005.03.28
申请人 NATIONAL UNIVERSITY CORPORATION OKAYAMA UNIVERSITY 发明人 MATSUMOTO YOHEI;MASAKI AKIRA
分类号 H03K19/173;G05F1/10;H01F38/14;H01L21/82;H01L27/118;H03K19/177 主分类号 H03K19/173
代理机构 代理人
主权项
地址