| 摘要 |
<P>PROBLEM TO BE SOLVED: To dissolve increase in parasitic capacitance load of word lines or reduction in yield due to wiring particles in a 6-transistor SRAM (static random access memory) memory cell having a horizontal memory cell layout. Ž<P>SOLUTION: The device includes: a plurality of word lines 351 aligned and disposed in the column direction in the second layer wiring; two or more pairs of bit lines 352 and 353 aligned and arranged in the row direction and a plurality of VDD power supply lines 354 disposed between each pair of bit lines in the third layer wiring; and a VSS power supply line formed by the wiring layer just above the bit lines in the fourth layer wiring. The VSS power supply line is connected to a CMOS type SRAM cell through an island-shaped VSS pattern formed by the wiring layer just below the VSS power supply line, and connection of the VSS power supply line to the island-shaped VSS pattern is attained by arrangement of a plurality of via parts per island-shaped VSS pattern. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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