CLOCK RESTRICTION CIRCUIT, SIGNAL OUTPUT CIRCUIT, AND SIGNAL INPUT CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a gated clock circuit applicable without being restricted by a target circuit.

SOLUTION: This gated clock circuit 10 restricts input of an operation clock CLK2 to an input circuit 30. The gated clock circuit 10 includes an XOR101 for outputting a signal of exclusive OR of an asynchronous signal ASYNC input into the input circuit 30 and a next signal DATA input into the input circuit 30 in the next clock, LAT102 and CGFF103 for outputting an output signal of the XOR101 according to a CLK2, and an AND104 for outputting a gated clock signal GCLK as a logical OR of the output of the CGFF103 and the CLK2.

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