| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To analyze the influence on parasitic capacitance by variation in manufacturing a contact structure with respect to a wiring structure having the contact structure. <P>SOLUTION: A sensitivity analyzing system includes a storage device, a parameter setting section, a capacitance calculating section and a sensitivity analyzing section. The storage device stores the wiring structure data indicating the wiring structure included in the semiconductor device. The wiring structure includes a main wiring formed on a certain wiring layer, and a contact structure electrically connected to the main wiring and extending in the direction of the semiconductor substrate from the main wiring. A plurality of parameters contribute to the parasitic capacitance of the wiring structure. The variation amount from a design value of each of the parameters caused by variation in manufacturing is defined within a predetermined range. The parameter setting section sets the variation amount of each parameter at a plurality of conditions within a predetermined range. The capacitance calculating section calculates the parasitic capacitance of the wiring structure in each of the plurality of conditions. The sensitivity analyzing section analyzes the response of the parasitic capacitance for the variation of each parameter based on the calculated parasitic capacitance. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
