| 摘要 |
<P>PROBLEM TO BE SOLVED: To solve a problem that, when the determine of a duty is present in an output clock in a conventional ADPLL circuit, a large error occurs in a finally-derived phase difference. <P>SOLUTION: This digital PLL circuit includes: a first counter for counting first clocks; a second counter for counting third clocks obtained by dividing the frequency of second clocks; a first phase detector for detecting a relative phase difference between the first and third clocks in accordance with a first comparison result obtained by comparing a delay clock of the third clock with the first clock and a second comparison result obtained by comparing a delay clock of the first clock with the third clock; a second phase detector for measuring the cycle of the second clocks; a phase error calculation part for calculating a phase difference between the first and third clocks in accordance with a value obtained by normalizing the detection result of the first phase detector by the detection result of the second phase detector, and values of the first and second counters; and a DCO for outputting the second clocks in accordance with the calculation result of the phase error calculation part. <P>COPYRIGHT: (C)2010,JPO&INPIT |
