发明名称 COMMUNICATION SYSTEM FOR SENDING AND RECEIVING DATA ONTO AND FROM A NETWORK AT A NETWORK FRAME RATE USING A PHASE LOCKED LOOP, SAMPLE RATE CONVERSION, OR SYNCHRONIZING CLOCKS GENERATED FROM THE NETWORK FRAME RATE
摘要 A communication system, source and destination ports of the communication system, and methodology is provided for transporting data in one of possibly three different ways. Data is transported across the network at a frame sample rate that can be the same as or different from the sample rate or master clock within the source port or the destination port. If the sample rate of the source port is known, the sample rate of the destination port can be created using a PLL within the destination port and simply employing a phase comparator in the source port. The phase comparator forwards the phase or frequency difference of the network transfer rate and the source sample rate to the destination port, which then generates a local clock equivalent to the source which then compiles audio data being played at the same rate in which it was sampled at the source. Where economically feasible, sample rate conversion can be used at the source. However, sample rate conversion at the destination is preferred if the source sample rate is forwarded across the network relative to the frame transfer rate of the synchronous network. The sample rate converter simply produces a play rate from the transmitted information at the destination. Again, however, sample rate conversion compares relative phase difference changes similar to the phase difference compared in the digital PLL mode. As a further alternative, sample rates within the source and destination ports can be derived from the network frame rate using fractional dividers in the source and destination ports.
申请公布号 KR20100085176(A) 申请公布日期 2010.07.28
申请号 KR20107013238 申请日期 2003.08.12
申请人 OASIS SILICON SYSTEMS 发明人 KNAPP DAVID J.;AKKIHAL SHIVANAND I.;MADDOX JOHN G.;GAALAAS JOSEPH B.;WINKELMANN MATTHIAS
分类号 H04L7/02;H04L12/56;H03M7/00;H04J3/06 主分类号 H04L7/02
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