发明名称 Self clock generation
摘要 A clock signal may be generated for a receiving circuit without requiring an external oscillator. A first digital circuit may convert a first signal edge at an input into a first clock signal at an output, and a second digital circuit, in feedback connection with the first digital circuit, may generate a second signal edge at the input based on the first clock signal at the output. Then, the first circuit may convert the second signal edge at the input to a second clock signal at the output. Thus, the first circuit and the second circuit, in combination, may generate a continuous stream of signal edges at the input and clock signals at the output. The second circuit may communicate with the controller circuit that may indicate that a subsequent clock signal is needed. The controller circuit may send commands and receive status from the receiving circuit.
申请公布号 US7764104(B2) 申请公布日期 2010.07.27
申请号 US20080034347 申请日期 2008.02.20
申请人 L3 COMMUNICATIONS CORPORATION 发明人 REINDL RICHARD MICHAEL;KIM BYUNGCHAE
分类号 H03K3/00 主分类号 H03K3/00
代理机构 代理人
主权项
地址