发明名称 Method of manufacturing a transistor and memory cell array
摘要 A transistor of an integrated circuit includes a first and second source/drain regions, a channel region connecting the first and second source/drain regions, and a gate electrode configured to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, that is defined in a top surface of a semiconductor substrate. The first and second source/drain regions extend at least to a depth d1, wherein the depth d1 is measured from the top surface of the substrate. A top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate in a distance to the top surface that is less than the depth d1.
申请公布号 US7763514(B2) 申请公布日期 2010.07.27
申请号 US20070851510 申请日期 2007.09.07
申请人 QIMONDA AG 发明人 VON KLUGE JOHANNES;TEGEN STEFAN
分类号 H01L21/336 主分类号 H01L21/336
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