| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory control circuit for reducing power consumption while the memory operates. SOLUTION: The memory control circuit controls operation of a DDR (Double Data Rate) memory, for example, as a memory and has: a three-state buffer for outputting signals which are input to a RASN (Row Address Strobe) terminal, CASN (Column Adress Strobe) terminal, a WEN (Write Enable) terminal, an ADD terminal and a BA (Bank address) terminal of the DDR memory respectively; and a generation circuit for generating an output enable signal to be input to the three-state buffer on the basis of a CSN (Chip Select) signal input to the CSN terminal of the DDR memory or an internal signal of the memory control circuit corresponding to the same signal. The three-state buffer is in an operation state during a period that the output enable signal is in an active state and has an output in a high-impedance state during a period that the output enable signal is in an inactive state. COPYRIGHT: (C)2010,JPO&INPIT
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