发明名称 ERROR ADDITION APPARATUS
摘要 PROBLEM TO BE SOLVED: To carry out a test without causing out-of-synchronization of frame on a test target apparatus side even when an error is added at high rate. SOLUTION: An error addition apparatus receives a data signal D having a frame structure with a specific signal prepended thereto, adds an error to the data signal D for output. The error addition apparatus also includes an error addition restriction part 30 for receiving a frame synchronization signal F indicating a timing when the head of the frame of the data signal D is input, and giving restrictions so that the error is added at a position other than a region of the specific signal. Thereby, error addition is not carried out to the specific signal. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010161630(A) 申请公布日期 2010.07.22
申请号 JP20090002485 申请日期 2009.01.08
申请人 ANRITSU CORP 发明人 FURUYA TAKASHI
分类号 H04L29/14 主分类号 H04L29/14
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